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Semiconductor Corporation
CS4215
General Description
The CS4215 is an MwaveTM audio codec.
16-Bit Multimedia Audio Codec
Features
* * * * * * * * * *
Sample Frequencies from 4 kHz to 50 kHz
16-bit Linear, 8-bit Linear, -Law, or A-Law Audio Data Coding The CS4215 is a single-chip, stereo, CMOS multimedia codec that supports CD-quality music, Programmable Gain for Analog Inputs FM radio-quality music, telephone-quality speech, and Programmable Attenuation for Analog Outputs On-chip Oscillators +5V Power Supply Microphone and Line Level Analog Inputs Headphone, Speaker, and Line Outputs On-chip Anti-Aliasing/Smoothing Filters Serial Digital Interface
Ordering Information: CS4215-KL 0C to 70C CS4215-KQ 0C to 70C CDB4215 Evaluation Board modems. The analog-to-digital and digital-to-analog converters are 64xoversampled delta-sigma converters with on-chip filters which adapt to the sample frequency selected. The +5V only power requirement makes the CS4215 ideal for use in workstations and personal computers. Integration of microphone and line level inputs, input and output gain setting, along with headphone and monitor speaker driver, results in a very small footprint.
44-pin PLCC 100-pin TQFP
CMOUT LINL LINR MINL MINR SDIN CLKIN CLKOUT XTL1IN XTL1OUT XTL2IN XTL2OUT PIO0 PIO1 D/C RESET PDN VA1 VA2 VD1 VD2 AGND1 AGND2 DGND1 DGND2 Control Interface and Registers Clock Generator 8 unsigned -law A-law decode + D/A Monitor Attenuator + Voltage Reference Serial Input/Output M U X Gain A/D A/D unsigned -law A-law encode TSIN TSOUT VREF MOUT1 MOUT2 D/A Output Attenuator Mute LOUTR LOUTL HEADC HEADR HEADL SDOUT SCLK FSYNC
This data sheet was written for Revision E CS4215 codecs and later. For differences between Revision E and previous versions, see Appendix A.
Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581
Copyright (c) Crystal Semiconductor Corporation 1993 (All Rights Reserved)
SEPT '93 DS76F2 1
CS4215
ANALOG CHARACTERISTICS( TA = 25C; VA1, VA2, VD1, VD2 = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2; Full Scale Input Sine wave, No Gain, No Attenuation 1 kHz; Conversion Rate = 48 kHz; No Gain, No Attenuation, SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to 20 kHz; Slave mode; Unless otherwise specified.)
Parameter * Symbol Min Typ Max Units
Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified.
ADC Resolution ADC Differential Nonlinearity Instantaneous Dynamic Range Total Harmonic Distortion Interchannel Isolation Interchannel Gain Mismatch Frequency Response (Note 1) Programmable Input Gain Gain Step Size Absolute Gain Step Error Offset Error with HPF = 0 (No Gain) Offset Error with HPF = 1 (Notes 1,2) (No Gain) Full Scale Input Voltage: Line Inputs (AC Coupled) Line Inputs (DC Coupled) Mic Inputs Line Inputs (AC Coupled) Line Inputs (DC Coupled) Mic Inputs (MLB=0) Mic Inputs (MLB=1) Mic Inputs Line Inputs Line Inputs Mic Inputs Line Inputs Mic Inputs Line to Line Inputs Line to Mic Inputs Line Inputs Mic Inputs (0 to 0.45 Fs) Line Inputs Mic Inputs IDR THD 16 80 72 -0.5 -0.2 19.8 0.250 2.50 2.50 (Note 3) 20 (Note 4) 1.9 84 78 80 60 1.5 150 10 400 0 0 0 0.28 2.8 2.8 100 2.1 0.9 0.012 0.032 0.5 0.5 +0.2 23.5 44 0.75 400 150 5 5 5 0.310 3.10 3.10 15 2.3 Bits LSB dB dB % % dB dB dB dB dB dB dB dB dB LSB
LSB Vpp Vpp Vpp ppm/C k pF V
Gain Drift Input Resistance Input Capacitance CMOUT Output Voltage (Maximum output current = 400 A)
Notes: 1. This specification is guaranteed by characterization, not production testing. 2. Very low frequency signals will be slightly distorted when using the HPF. 3. Input resistance is for the input selected. Non-selected inputs have a very high (>1M) input resistance. 4. DC current only. If dynamic loading exists, then CMOUT must be buffered or the performance of ADC's and DAC's may be degraded. * Parameter definitions are given at the end of this data sheet. MwaveTM is a trademark of the IBM Corporation. 2 Specifications are subject to change without notice. DS76F2
CS4215
ANALOG CHARACTERISTICS
Parameter *
(Continued) Symbol Min Typ Max Units
Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified.
DAC Resolution DAC Differential Nonlinearity Total Dynamic Range Instantaneous Dynamic Range (OLB = 1) Total Harmonic Distortion (OLB = 1) Interchannel Isolation Interchannel Gain Mismatch Frequency Response (Note 1) Programmable Attenuation Attenuation Step Size Absolute Attenuation Step Error Offset Voltage Line Out (All Outputs) TDR IDR THD 16 80 -0.5 0.2 2.55 3.6 7.3 1.8 1.8 3.6 (22 kHz to 100 kHz) Line Out 95 85 80 40 1.5 10 2.8 4.0 8.0 2.0 2.0 4.0 100 -60 0.9 0.025 0.2 0.32 0.5 0.5 +0.2 -94.7 0.75 3.08 4.4 8.8 2.2 2.2 4.4 1 Bits LSB dB dB % % % dB dB dB dB dB dB dB dB mV Vpp Vpp Vpp Vpp Vpp Vpp ppm/C Degree dB
Line Out (Note 5) Headphone Out (Note 6) Speaker Out (Note 6) Line Out (Note 5) Headphone Out (Note 6) Line Out Headphone (0 to 0.45 Fs) (All Outputs)
Full Scale Output Voltage Line Output (Note 5) with OLB = 0 Headphone Output (Note 6) Speaker Output-Differential (Note 6) Full Scale Output Voltage Line Output (Note 5) with OLB = 1 Headphone Output (Note 6) Speaker Output-Differential (Note 6) Gain Drift Deviation from Linear Phase Out of Band Energy
Power Supply
Power Supply Current Power Supply Rejection (Note 7) Operating Power Down (1 kHz) 110 0.5 40 140 2 mA mA dB
Notes: 5. 10 k, 100 pF load. Headphone and Speaker outputs disabled. 6. 48 , 100 pF load. For the headphone outputs, THD with 10k, 100pF load is 0.02%. 7. Typically, 50% of the power supply current is supplied to the analog power pins (VA1, VA2) and 50% is supplied to the digital power pins (VD1, VD2). Values given are for unloaded outputs.
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CS4215
A/D Decimation Filter Characteristics
Parameter Passband Frequency Response Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Group Delay Variation vs. Frequency (Fs is conversion freq.) Symbol Min 0 -0.5 0.45Fs 0.55Fs 74 Typ 16/Fs Max 0.45Fs +0.2 0.1 0.55Fs 0.0 Units Hz dB dB Hz Hz dB s s
D/A Interpolation Filter Characteristics
Parameter Passband Frequency Response Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Group Delay Variation vs. Frequency (Fs is conversion freq.) Symbol Min 0 -0.5 0.45Fs 0.55Fs 74 Typ 16/Fs Max 0.45Fs +0.2 0.1 0.55Fs 0.1/Fs Units Hz dB dB Hz Hz dB s s
DIGITAL CHARACTERISTICS (TA = 25C; VA1, VA2, VD1, VD2 = 5V)
Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage at I0 = -2.0 mA Low-level Output Voltage at I0 = 2.0 mA Input Leakage Current Output Leakage Current (Digital Inputs) (High-Z Digital Outputs) Symbol VIH VIL VOH VOL Min (VD1,VD2)-1.0 -0.3 (VD1,VD2)-0.2 Max (VD1,VD2)+0.3 1.0 0.1 10 10 Units V V V V A A
4
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CS4215
SWITCHING CHARACTERISTICS (TA = 25C; VA1, VA2, VD1, VD2 = +5V, outputs loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = VD1, VD2)
Parameter SCLK period SCLK high time SCLK low time Input Setup Time Input Hold Time Input Transition Time Output delay SCLK to TSOUT Output to Hi-Z state Output to non-Hi-Z Input Clock Frequency Input Clock (CLKIN) low time Input Clock (CLKIN) high time Sample rate RESET low time (Note 11) Fs Timeslot 8, bit 0 Timeslot 1, bit 7 Crystals CLKIN (Note 10) 10% to 90% points tpd1 tpd2 thz tnz Master Mode, XCLK = 1 (Note 8) Slave Mode (XCLK = 0) Slave Mode, XCLK = 0 (Note 9) Slave Mode, XCLK = 0 (Note 9) Symbol tsckw tsckw tsckh tsckl ts1 th1 Min 80 25 25 15 10 15 1.024 30 30 4 500 Typ 1/(Fs*bpf) Max 10 28 30 12 27 13.5 50 Units s ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns kHz ns
Notes: 8. In Master mode with BSEL1,0 set to 64 or 128 bits per frame (bpf), the SCLK duty cycle is 50%. When BSEL1,0 is set to 256 bpf, SCLK will have the same duty cycle as CLKOUT. See Internal Clock Generation section. 9. In Slave mode, FSYNC and SCLK must be derived from the master clock running the codec (CLKIN, XTAL1, XTAL2). 10. Sample rate specifications must not be exceeded. 11. After powering up the CS4215, RESET should be held low for 50 ms to allow the voltage reference to settle.
t s1 FSYNC TSIN TSOUT t FSYNC out pd1 t t sckl t sckw pd1 in t t t h1 t s1 t h1
pd2
pd2
t sckh SCLK t
s1
t
h1 TS 1, Bit 6 t pd1 TS 8, Bit 0
SDIN t SDOUT t pd1 nz
TS 1, Bit 7
TS 1, Bit 7
TS 1, Bit 6
TS 8, Bit 0 t hz
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CS4215
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.)
Parameter Power Supplies: Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Warning: (Power Applied) Symbol Digital VD1,VD2 Analog VA1,VA2 (Except Supply Pins) Min -0.3 -0.3 -0.3 -0.3 -55 -65 Max 6.0 6.0 10.0 (VA1, VA2)+0.3 (VD1, VD2)+0.3 +125 +150 Units V V mA V V C C
Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
spect to 0V.) Parameter Power Supplies: Operating Ambient Temperature Note:
(AGND, DGND = 0V, all voltages with reMin 4.75 4.75 0 Typ 5.0 5.0 25 Max 5.25 5.25 70 Units V V C
Symbol Digital (Note 8) VD1,VD2 Analog (Note 8) VA1,VA2 TA
8. VD - VA must be less than 0.5 Volts (one diode drop).
6
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CS4215
F errite B e ad + 5 V D ig ita l S upply 1 uF + 0.1 uF 3 0.4 7 uF M icroph one In pu t R ight 0 .01 u F NPO HEADR HEADL 30 1 2 1/2W 0.47 uF M icrophon e HEADC 150 29 31 150 15 VD1 MINR 8 VD2 0.1 u F + 1 uF + 5V A n alog S u pp ly
24
VA2
23
VA1 M O U T1 M O U T2 28 27 1 2 1/2W > 3 2
H e a dph one Jack >48
17
MINL
In put Le ft 0.01 u F NPO
LOUTR
33
600
+ > 1.0 uF 40 k
0.00 22 u F NPO 32 600
LO UTL 19
+ > 1.0 uF + 0 .1 u F 10 uF 40 k
T o O ption al Input B uffers 0 .47 uF
CMOUT
C S4215
VR EF
0.00 22 u F NPO 21
X T L2IN 16 LINR S e e Lin e Leve l Inp uts S ection 18
10
40pF 16.934 4 M H z
X T L2O U T
11
40pF
6 LIN L X T L1IN 7
40pF 24.576 M H z 20 k +5v
40pF
X T L1O U T Refer to the Analog Inputs section for terminating unused line and mic inputs. All other unused inputs should be tied to GND. All NC pins should be left floating.
SDIN C L K IN CLKO UT RESET PDN
1 4 5 12 13 44
SDOUT
VD1 47 k 36 PIO0 37 PIO1 TSOUT TSIN D /C S C LK FSYNC AGND1 22 AG ND2 25 DG ND1 2 DGND2 9
41 40
35 43 42
C o ntroller
20 k
20k
Note: AGND and DGND pins must be on the same ground plane. Figure 1. Recommended Connection Diagram DS76F2 7
CS4215 FUNCTIONAL DESCRIPTION Overview The CS4215 has two channels of 16-bit analogto-digital conversion and two channels of 16-bit digital-to-analog conversion. Both the ADCs and the DACs are delta-sigma converters. The ADC inputs have adjustable input gain, while the DAC outputs have adjustable output attenuation. Special features include a separate microphone input with a 20 dB programmable gain block, an optional 8-bit -law or A-law encoder/decoder, pins for two crystals to set alternative sample rates, direct headphone drive and mono speaker drive. Control for the functions available on the CS4215, as well as the audio data, are communicated to the device over a serial interface. Separate pins for input and output data are provided, allowing concurrent writing to and reading from the device. Data must be continually written for proper operation. Multiple CS4215 devices may be attached to the same data lines. Analog Inputs Figure 1, the recommended connection diagram, shows examples of the external analog circuitry recommended around the CS4215. An internal multiplexer selects between line level inputs and microphone level inputs. Input filters using a 150 resistor and a .01 F NPO capacitor to ground are required to isolate the input op-amps from, and provide a charge reserve for, the switched-capacitor input of the codec. The RC values may be safely changed by a factor of two. The HPF bit in Control Time Slot 2 provides a high pass filter that will reduce DC offset on the analog inputs. Using the high pass filter will cause slight distortions at very low frequencies. Unused analog inputs that are not selected have a very high input impedance, so they may be tied to AGND directly. Unused analog inputs that are selected should be tied to AGND through a 0.1uF capacitor. This prevents any DC current flow. Line Level Inputs LINL and LINR are the line level input pins. These pins are internally biased to the CMOUT voltage. Figure 2 shows a dual op-amp buffer which combines level shifting with a gain of 0.5 to attenuate the standard line level of 2 Vrms to
56 pF
0.47 uF Line In Right
20 k
10 k _ +
150 0.01 uF NPO
LINR (pin 16)
Example Op-Amps are LT1013
5k 0.47 uF
0.47 uF
CMOUT (pin 19)
Line In Left
0.47 uF
20 k
+ _ 10 k
150
LINL (pin 18) 0.01 uF NPO
56 pF Op-amps are run from VA1, VA2 and AGND.
Figure 2. DC Coupled Input.
0.47 uF Line In Right 150 LINR (pin 16) 0.01 uF NPO NPO 0.01 uF Line In Left 0.47 uF 150 LINL (pin 18)
Figure 3. AC Coupled Input.
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CS4215
R6 2.2 k C6 VA+ R4 22.1 k C4 560 pF NPO 8 4 C5 R5 50 k R2 50 k 5 6 1 U2 MC33078 or MC33178 + C7 1 uF C45 R57 150 NPO C46 0.01 uF Microphone Input Left (pin 17) C2 + 1 uF C8 0.1 uF C48 0.47 uF R56 150 C47 Microphone Input Right (pin 15) NPO 0.01 uF
+ 10 uF
1 uF + MINR
2 3
CMOUT
MINL (Mono)
7 A =20 dB C1 560 pF NPO
0.47 uF
2.2 k R3 10 uF + C3
22.1 k R1
Figure 4. Optional Microphone Input Buffer
1 Vrms. The CMOUT reference level is used to level shift the signal. This level shifting allows the line inputs to be DC coupled into the CS4215. Minimum ADC offset results when the line inputs are DC coupled (see Analog Characteristics Table). Figure 3 shows an AC coupled input circuit for signals centered around 0 Volts. The anti-aliasing RC filter presents a low impedance at high frequencies and should be driven by a low impedance source. Microphone Level Inputs Internal amplifiers with a programmable 20 dB gain block are provided for the microphone level inputs, MINR and MINL. Figure 4 shows a single-ended input microphone pre-amplifier stage with a gain of 23 dB. AC coupling is mandatory for these inputs since any DC offset on the input will be amplified by the codec.
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The 20 dB gain block may be disabled using the MLB bit in Control Time Slot 1. When disabled, the inputs become line level with full scale inputs of 1 Vrms. Adjustable Input Gain The signals from the microphone or the line inputs are routed to a programmable gain circuit which provides up to 22.5 dB of gain in 1.5 dB steps. Level changes only take effect on zero crossings to minimize audible artifacts, often referred to as "zipper noise". The requested level change is forced if no zero crossing is found after 511 frames (10.6 ms at a 48 kHz frame rate). A separate zero crossing detector exists for each channel. Analog Outputs The analog outputs of the DACs are routed via an attenuator to a pair of line outputs, a pair of
9
CS4215 headphone outputs and a mono monitor speaker output. Output Level Attenuator The DAC outputs are routed through an attenuator, which provides 0 dB to 94.5 dB of attenuation, adjustable in 1.5 dB steps. Level changes are implemented using both analog and digital attenuation techniques. Level changes only take effect on zero crossings to minimize audible artifacts. The requested level change is forced if an analog zero crossing does not occur within 511 frames (10.6 ms at a 48 kHz frame rate). A separate zero crossing detector exists for each channel. Line Outputs LOUTR and LOUTL output an analog signal, centered around the CMOUT voltage. The minimum recommended load impedance is 8 k. Figure 1 shows the recommended 1.0 F DC blocking capacitor with a 40 k resistor to ground. When driving impedances greater than 10 k, this provides a high pass corner of 20 Hz. These outputs may be muted. Headphone Outputs Input Monitor Function HEADR and HEADL output an analog signal, centered around the HEADC voltage. The default headphone output level (OLB = 0) contains an optional 3 dB gain over the line outputs which provides reasonable listening levels, even with small amplitude digital sources. These outputs have increased current drive capability and can drive a load impedance as low as 48 . External 12 series resistors reduce output level variations with different impedance headphones. The common return line from driving headphones should be connected to HEADC, which is biased to the CMOUT voltage. This removes the need for AC coupling, and also controls where the return currents flow. All three head10
phone output lines are short-circuit protected. These outputs may be muted. Speaker Output MOUT1 and MOUT2 differentially drive a small loudspeaker, whose impedance should be greater than 32 . The signal is a summed version of the right and left line output, tapped off prior to the mute function, but after the attenuator. The speaker output may be independently muted. With OLB = 0, the speaker output also contains a 3 dB gain over the line outputs. When OLB = 1, the speaker outputs are driven at the same level as the line outputs. Some small speakers distort heavily when presented with low frequency energy. A high-pass filter helps eliminate the low frequency energy and can be implemented by AC coupling both speaker terminals with a resistor to ground, on the speaker side of the DC blocking capacitors. The values selected would depend on the speaker chosen, but typical values would be 22 F for the capacitors, with the positive side connected to the codec, and 50 k resistors. This circuit is contained on the CDB4215 evaluation board as shown in the end of this data sheet.
To allow monitoring of the input audio signal, the output of the ADCs can be routed through a monitor path attenuator, then digitally mixed into the input data for the DACs (see the front page block diagram). Changes in the input gain or output level settings directly affect the monitor level. If full scale data from the ADCs is added to full scale digital data from the serial interface, clipping will occur. Calibration Both output offset voltage and input offset error are minimized by an internal calibration cycle. At least one calibration cycle must be invoked
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CS4215
FSYNC SCLK CLKOUT 8.5 CLKOUT's PIO Read 11 CLKOUT's PIO Write
Data Mode -Read and Write
TSIN SCLK
PIO Read 1 SCLK
Control Mode - Read Only
Notes:
1. DATA MODE READ - The data is sent out via SDOUT on the next frame. 2. CONTROL MODE READ - The data is sent out, via SDOUT, the same frame. 3. DATA MODE READ, WRITE - are tied to the rising edge of FSYNC and CLKOUT. They are independent of SCLK. 4. CONTROL MODE READ - The PIO pins are sampled by a rising edge of SCLK.
Figure 5. PIO Pin Timing
after power up. A calibration cycle will occur immediately after leaving the reset state. A calibration cycle will also occur immediately after going from control mode to data mode (D/C going high). When powering up the CS4215, or exiting the power down state, a minimum of 50 ms must occur, to allow the voltage reference to settle, before initiating a calibration cycle. This is achieved by holding RESET low or staying in control mode for 50 ms after power up or exiting power down mode. The input offset error will be calibrated for whichever input channel is selected (microphone or line, using the IS bit). Therefore, the IS bit should remain steady while the codec is calibrating, although the other bits input to the codec are ignored. Calibration takes 194 FSYNC cycles and SDOUT data bits will be zero during this period. The A/D Invalid bit, ADI (bit 7 in data time slot 6), will be high during
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calibration and will go low when calibration is finished. Parallel Input/Output Two pins are provided for parallel input/output. These pins are open drain outputs and require external pull-up resistors. Writing a zero turns on the output transistor, pulling the pin to ground; writing a one turns off the output transistor, which allows an external resistor to pull the pin high. When used as an input, a one must be written to the pin, thereby allowing an external device to pull it low or leave it high. These pins can be read in control mode and their state is recorded in Control Register 5. These pins can be written to and read back in data mode using Data Register 7. Figure 5 shows the Parallel Input/Output timing.
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CS4215 Clock Generation The master clock operating the CS4215 may be generated using the on-chip crystal oscillators, or by using an external clock source. In all data modes SCLK and FSYNC must be synchronous to the selected master clock. If the master clock source stops, the digital filters will power down after 5 s to prevent overheating. If FSYNC stops, the digital filters will power down after approximately 1 FSYNC period. The CS4215 will not enter the total power down state. Internal Clock Generation Two external crystals may be attached to the XTL1IN, XTL1OUT, XTL2IN and XTL2OUT pins. Use of an external crystal requires additional 40 pF loading capacitors to digital ground (see Figure 1). XTAL1 oscillator is intended for use at 24.576 MHz and XTAL2 oscillator is intended for use at 16.9344 MHz, although other frequencies may be used. The gain of the internal inverter is slightly higher for XTAL1, ensuring proper operation at >24 MHz frequencies. The crystals should be parallel resonant, fundamental mode and designed for 20 pF loading (equivalent to a 40 pF capacitor on each leg). If XTAL1 or XTAL2 is not selected as the master clock, that particular crystal oscillator is powered down to minimize interference. If a crystal is not needed, the XTL-IN pin should be grounded. An example crystal supplier is CAL Crystal, telephone number (714) 991-1580. FSYNC and SCLK must be synchronous to the master clock. When using the codec in slave mode with one of the crystals as master clock, the controller must derive FSYNC and SCLK from the crystals, i.e. via CLKOUT. Note that CLKOUT will stop in a low condition within two periods after D/C goes low. An internally generated clock which is 256 times the sample rate (FSYNC rate) is output (CLKOUT) for potential use with an external AES/EBU transmitter, or another CS4215. No glitch occurs on CLKOUT when selecting alternate clock sources. CLKOUT will stop in a low condition within two periods after D/C goes low, assuming one of the crystal oscillators is selected, or either CLKIN or SCLK is the master clock source and is continuous. The duty cycle of CLKOUT is 50% if the master clock is one of the crystal oscillators and the DFR bits are 0, 1, 2, 6 or 7. If the DFR bits are 3 or 5, the duty cycle is 33% (high time). If the DFR bits are 4 then CLKOUT has the timing shown in Figure 6. If the master clock is SCLK or CLKIN, the duty cycle of CLKOUT will be the same as the master clock source.
1 2 1 3 1 2 1 3
1/(128 x FSYNC)
1/(128 x FSYNC)
Figure 6. CLKOUT duty cycle using the on-chip crystal oscillator when DFR = 4 ( typically FSYNC = 37.8 kHz)
External Clock An external clock input pin (CLKIN) is provided for potential use with an external AES/EBU receiver, or an already existing system clock. When MCK2 = 0, the input clock must be exactly 256 times the sample rate, and FSYNC and SCLK must be synchronous to CLKIN. When MCK2 = 1 the DFR bits allow various divide ratios off the CLKIN frequency. Alternatively, an external high frequency clock may be driven into XTL1IN or XTL2IN. The correct clock source must be selected using the MCK bits. Manipulating DFR bits will allow various divide ratios from the clock to be seDS76F2
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CS4215 lected. SCLK and FSYNC must be synchronous to the external clock. As a third alternative, SCLK may be programmed to be the master clock input. In this case, it must be 256 times Fs. Serial Interface The serial interface of the CS4215 transfers digital audio data and control data into and out of the device. Multiple CS4215 devices may share the same data lines. DSP's supported include the Motorola 56001 in network mode and a subset of the `CHI' bus from AT&T/Intel. Serial Interface Signals Figure 7 shows an example of two CS4215 devices connected to a common controller. The Serial Data Out (SDOUT) and Serial Data In (SDIN) lines are time division multiplexed between the CS4215s. The serial interface clock, SCLK, is used for transmitting and receiving data. SCLK can be generated by one of the CS4215s, or it can be input from an external SCLK source. When generated by an external source, SCLK must be synchronous to the master clock. Data is transmitted on the rising edge of SCLK and is received on the falling edge of SCLK. The SCLK frequency is always equal to the bit rate. The Frame Synchronizing signal (FSYNC) is used to indicate the start of a frame. It may be output from one of the CS4215s, or it may be generated from an external controller. If FSYNC is generated externally, it must be high for at least 1 SCLK period, and it must fall at least 2 SCLKs before the start of a new frame (see Figure 8). It must also be synchronous to the master clock. The frequency of FSYNC is equal to the system sample rate (see Figure 8). Each CS4215 requires 64 SCLKs to transfer all the data. The SCLK frequency can be set to 64, 128,
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Controller
or 256 bits per frame, thereby allowing for 1, 2 or 4 CS4215s connected to the same bus. In a typical multi-part scenario, one CS4215 (the master) would generate FSYNC and SCLK, while the other CS4215s (the slaves) would receive FSYNC and SCLK. The CLKOUT of the master would be connected to the CLKIN of each slave device as shown in Figure 7. Then, the master device would be programmed for the desired sample frequency (assuming one of the crystals is selected as the clock source), the number of bits per frame, and for SCLK and FSYNC to be outputs. The slave devices would be programmed to use CLKIN as the clock source, the same number of bits per frame, and for SCLK and FSYNC to be inputs. Since CLKOUT is al-
SCLK SCLK SDIN SDOUT FSYNC FSYNC TSIN TSOUT D/C D/C PDN SDIN SDOUT
CS4215 XTL1IN XTL1OUT
A XTL2IN XTL2OUT Master CLKOUT
RESET
CS4215 SCLK SDIN SDOUT FSYNC B TSIN TSOUT D/C PDN RESET Slave CLKIN
Figure 7. Multiple CS4215's
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CS4215
T1 FSYNC TSINA
TSn
TS8
TS1
TS2
TS3
TS8
TS1
TS2
TS7
TS8
DEVICE A TSOUTA TSINB TSOUTB
DEVICE B
T1 TSn
1/Frame Rate or 1/System Sample Rate Time slot numbers
Figure 8. Serial Interface Timing for 2 CS4215's
1 SCLK FSYNC TSIN DATA 0 7 6 1 0 7 6 1 0 7 6 1 0 7 6 5 2 8 9 10 16 17 18 64 65 66 67 68
TS1 TSOUT
TS2
TS3
TS8
TS1
Figure 9. Frame Sync and Bit Offset Timing
1 SCLK FSYNC, TSIN A TSOUT A, TSIN B TSOUT B SDIN SDOUT _ D/C
2
3
4
64 65 66 67 68 128 1
2
3
4
5
64 65 66
Control to A
Control to B
Control to A Control from A Control from B
Control Mode
Figure 10. Control Mode Timing for 2 CS4215's
14
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CS4215 ways 256 times the sample frequency and scales with the selected sample frequency on the master, the slave devices will automatically scale with changes in the master codec's sample frequency. CS4215s are time division multiplexed onto the bus using the Time Slot Out (TSOUT) and Time Slot In (TSIN) signals. TSOUT is an output signal that is high for one SCLK bit time, and indicates that the CS4215 is about to release the bus. TSIN is an input signal that informs the CS4215 that the next time slot is available for it to use. The first device in the chain uses FSYNC as its TSIN signal. All subsequent devices use the TSOUT of the previous device as its TSIN input. TSIN must be high for at least 1 SCLK period and fall at least 2 SCLKs before start of a new frame. Serial Interface Operation The serial interface format has a variable number of time slots, depending on the number of CS4215s attached to the bus. All time slots have 8 bits. Each CS4215 requires 8 time slots (64 bits) to communicate all data (see Figure 9). CONTROL MODE The Control Mode is used to set up the CS4215 for subsequent operation in Data Mode by loading the internal control registers. Control mode is asserted by bringing D/C low. If D/C is low during power up, then the CS4215 will enter control mode immediately. The SCLK and FSYNC pins are tri-stated, and the CS4215 will receive SCLK and FSYNC from an external source. If the CS4215 is in master mode (SCLK and FSYNC are outputs) and D/C is brought low, then SCLK & FSYNC will continue to be driven for a minimum of 4 and a maximum of 12 SCLKs, if the ITS bit = 0. If ITS is 1, SCLK and FSYNC will three-state immediately after D/C goes low. If D/C is brought low when the codec is programmed as master with ITS=0, the codec will
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timeout and release FSYNC and SCLK within 100s. The values in the control registers for control of the serial ports are ignored in control mode. The data received on SDIN is stored into the control registers which have addresses matching their time slots. The data in the registers is transmitted on SDOUT with the time slot equal to the register number (see Figure 10). The steps involved when going from data mode to control mode and back are shown in the flow chart in Figure 11.
Control Formats The CS4215 control registers have the functions and time slot assignments shown in Table 1. The register address is the time slot number when D/C is 0. Reserved bits should be written as 0 and could be read back as 0 or 1. When comparing data read back, reserved bits should be masked. The SDOUT pin goes into a high-impedance state prior to Time Slot 1 and after Time Slot 8. The data listed below the register is its reset state. The parallel port register is used to read and write the two open-drain input/output pins. The outputs are all set to 1 on RESET. PIO bits are read only in control mode. Note that, since PIO signals are open drain signals, an external device
Time slot 1 2 3 4 5 6 7 8 Description Status Data Format Serial Port Control Test Parallel Port RESERVED Revision RESERVED
Table 1. Control Registers
15
CS4215 may drive them low even when they have been programmed as highs. Therefore, the value read back may differ from the value written. In the data mode, (D/C=1), this register can be read and written to through the serial port as part of the Input Settings Registers. In control mode, (D/C=0) these bits can only be read.
16
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CS4215
Lower output level to maximum attenuation Mute the speaker output Set D/C low
Wait at least 12 SCLK periods for FSYNC and SCLK to three-state
Y
Codec programmed for Master mode & ITS=0? N Set external controller to drive SCLK and FSYNC into the codec
1 This is a software design choice,
not a run-time conditional branch.
Poll for CLB=0? Y
1
N
n=5
Send valid control information with CLB=0 Read back and verify control information. Mask off reserved bits N
Send valid control information with CLB=0
n=n-1
CLB=0? Y
n = 0? Y
N
Set CLB=1 and send at least two more frames of valid 2 control information
2
Set external controller to receive SCLK and FSYNC from the codec
Y
Is codec programmed for Master mode? N Set D/C high.
This will cause the codec to ignore any further bus activity. The SDOUT pin will be held in the high impedance state after transmitting 1 frame with CLB=1
Transmit/receive data with attenuated outputs and muted speaker for 194 FSYNC cycles while codec executes offset calibration Transmit/receive audio data with desired level settings
Figure 11. Control Mode Flow Chart DS76F2 17
CS4215
Control Time Slot 1, Status Register
D7 D6 0 0 D5 1 1 VALUE 1 0 D4 MLB 0 D3 OLB 0 D2 CLB 1 D1 X D0 X
Register Reset (R)
BIT RSRV CLB OLB NAME Reserved Bits Control Latch Bit Output Level Bit
0 0
RSRV
1 MLB Microphone Level 0 1
FUNCTION Must be written as 0. R Ensures proper transition between control and data mode. R Line full scale outputs are 2.8 Vpp (1Vrms) Headphone full scale output is 4.0 Vpp. Speaker full scale output is 8.0 Vpp. Line and Headphone full scale outputs are 2.0 Vpp. Speaker full scale output is 4.0 Vpp. R 20 dB Fixed Gain Enabled Full scale microphone inputs are 0.288 Vpp. 20 dB Fixed Gain Disabled Full scale inputs are 2.88 Vpp.
Control Time Slot 2, Data Format Register
D7 D6 X D5 0 D4 0 D3 0 D2 ST 0 D1 DF1 0 D0 DF0 1
Register Reset (R)
BIT DF1-0 NAME Data Format Selection
HPF 0
RSRV DFR2 DFR1 DFR0
ST DFR2-0
Stereo Bit Data Conversion Frequency Selection
VALUE 00 01 10 11 0 1
0 1 2 3
R
R
0 0 0 0 1 1 1 1 RSRV HPF Reserved Bit High Pass Filter
0 0 1 1 0 0 1 1 0 1
0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7
R
R
FUNCTION 16-bit 2 -complement linear. 8-bit -Law. 8-bit A-Law. 8-bit unsigned linear. Mono Mode. Stereo Mode. XTAL1(kHz) XTAL2 (kHz) CLKIN (/) 24.576 MHz 16.9344 MHz 3072 8 5.5125 1536 16 11.025 896 27.42857 18.9 768 32 22.05 448 NA 37.8 384 NA 44.1 512 48 33.075 2560 9.6 6.615 Must be written as 0 Disabled. Enabled. A Digital High Pass Filter is used to force the ADC DC offset to zero.
's
18
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CS4215
Control Time Slot 3, Serial Port Control Register
D7 D6 0 D5 0 VALUE 0 1 0 1 BSEL1-0 Select Bit Rate 00 01 10 11 000 0 0 0 1 ITS Immediate ThreeState 0 1 1 0 0 1 1 0 1 0 0 1 2 3 0 1 2 3 4 D4 0 D3 1 D2 0 D1 0 D0 XEN 1
Register Reset (R)
BIT XEN XCLK
ITS 0
MCK2 MCK1 MCK0 BSEL1 BSEL0 XCLK
NAME Transmitter Enable Transmit Clock
R R
R R
MCK2-0
Clock Source Select
R
FUNCTION Enable the serial data output. Disable (high-impedance state) serial data output. Receive SCLK and FSYNC from external source SLAVE Mode Generate SCLK and FSYNC MASTER Mode 64 bits per frame. 128 bits per frame. 256 bits per frame. Reserved. SCLK is master clock, 256 bits per frame. BSEL must equal 2, and XCLK must equal 0. XTAL1, 24.576 MHz, is clock source. XTAL2, 16.9344 MHz, is clock source. CLKIN is clock source, and must be 256xFs. CLKIN is clock source, DFR2-0 select sample frequency. SCLK and FSYNC three-state up to 12 clocks after D/C goes low. SCLK and FSYNC three-state immediately after D/C goes low.
Control Time Slot 4, Test Register
D7 D6 0 D5 TEST 0 0 VALUE 0 1 0 1 0 0 0 D4 D3 D2 D1 ENL 0 D0 DAD 0
Register Reset (R)
BIT DAD ENL TEST NAME Loopback Mode Enable Loopback Testing Test bits
FUNCTION R Digital-Digital Loopback. Digital-Analog-Digital Loopback. R Disable. Enable. The TEST bits must be written as zero, otherwise special factory test modes may be invoked.
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19
CS4215
Control Time Slot 5, Parallel Port Register
D7 D6 PIO0 1 X VALUE 11 3 X D5 D4 D3 X D2 X D1 X D0 X
Register Reset (R)
BIT RSRV PIO1-0 NAME Reserved Bits Parallel I/O Bits
PIO1 1
RSRV
FUNCTION Must be written as 0. R See the Parallel Input/Output Section.
Control Time Slot 6, Reserved Register
D7 D6 X D5 X VALUE D4 X D3 X D2 X D1 X D0 X
Register Reset (R)
BIT RSRV NAME Reserved Bits X
RSRV
FUNCTION Must be written as 0.
Control Time Slot 7, Version Register
D7 D6 X D5 X D4 X D3 0 D2 0 D1 1 D0 0
Register Reset (R)
BIT VER3-0 NAME Device Version Number Reserved Bits X
RSRV
VER3 VER2 VER1 VER0
VALUE 0000 0 0001 1 0010 2
RSRV
FUNCTION "C". See Appendix A. "D". See Appendix A. R "E". This Data Sheet Must be written as 0.
Control Time Slot 8, Reserved Register
D7 D6 X D5 X VALUE D4 X D3 X D2 X D1 X D0 X
Register Reset (R)
BIT RSRV NAME Reserved Bits X
RSRV
FUNCTION Must be written as 0.
20
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CS4215
128 1 SCLK FSYNC, TSIN A TSOUT A, TSIN B TSOUT B SDIN SDOUT _ D/C Data to A Data from A Data Mode Data to B Data from B Data to A Data from A 2 3 4 64 65 66 67 68 69 128 1 2 3 4
Figure 12. Data Mode Timing for 2 CS4215's
DATA MODE The data mode is used during conversions to pass digital data between the CS4215 and external devices. The frame sync rate is equal to the value of the conversion frequency set by the DFR2-DFR0 bits of the Data Format register. Each frame has either 64, 128, or 256 bit times depending on the BSEL bits in the Serial Control register. Control of gain, attenuation, input selection and output muting are embedded in the data stream. Data Formats
+FS
Time slot 1 2 3 4 5 6 7 8
Description Left Audio MS8 bits Left Audio LS8 bits Right Audio MS8 bits Right Audio LS8 bits Output Setting Output Setting Input Setting Input Setting
Table 2. Data Registers
All time slots contain 8 bits. The MSB of the data is transmitted/received first. The CS4215 data registers have the functions and time slot assignments shown in Table 2. The register address is the time slot number when D/C is 1. The SDOUT pin goes into a high-impedance state prior to time slot 1 and after Time Slot 8 (see Figure 12). The CS4215 supports four audio data formats: 16-bit 2's-complement linear, 8-bit unsigned linear, 8-bit A-Law, and 8-bit -Law. Figure 13 illustrates the transfer characteristic for 16-bit and 8-bit linear formats. Note that a digital code
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ANALOG VALUE
0
-FS 8-bit 0 unsigned: 16-bit -32768 2's comp:
65 -16384
128 0 DIGITAL CODE
191 16384
255 32767
Figure 13. Linear Data Formats 21
CS4215 (12) bits for the DACs and compressed from the upper 13 (12) bits to 8 bits for the ADCs. Data Time Slot 1&2, Left Channel Audio Data
ANALOG VALUE 0
+FS
Time slot 1 and 2 contain audio data for the left channel. In mono modes, only the left channel data is used, however both the right and left output DACs are driven. In 8-bit modes, only time slot 1 is used for the data.
15h 3Fh 55h/D5h 7Fh/FFh DIGITAL CODE 95h BFh AAh 80h
-FS A-Law: 2Ah u-Law: 00h
Data Time Slot 3&4, Right Channel Audio Data Time slot 3 and 4 contains audio data for the right channel. In mono modes, the right ADC outputs zero and the right DAC uses the left digital data. In 8-bit modes, only time slot 3 is used for the data. Figure 15 summarizes all the time slot bit allocations for the 4 data modes and for control mode. Reset RESET going low causes all the internal control registers to be set to the states shown with each register description. RESET must be brought low and high at least once after power up. RESET returning high causes the CS4215 to execute an offset calibration cycle. RESET or D/C returning high should occur at least 50 ms after the power supply has stabilized to allow the voltage reference to settle.
Figure 14. Companded Data Formats
of 128 (80 Hex) is considered analog zero for the 8-bit unsigned format. A non-linear coding scheme is used for the companded formats as shown in Figure 14. This scheme is compatible with CCITT G.711. Companding uses more precision at lower amplitudes at the expense of less precision at higher amplitudes. -Law is equivalent to 13 bits at low signal levels and A-Law is equivalent to 12 bits. This low-level dynamic range is obtained at the expense of large-signal dynamic range which, for both -Law and A-Law, is equivalent to 6 bits. The CS4215 internally operates at 16 bits. The companded data is expanded to the upper 13
Data Time Slot 5, Output Setting
D7 D6 LE 0 D5 LO5 1 D4 LO4 1 D3 LO3 1 D2 LO2 1 D1 LO1 1 D0 LO0 1
Register Reset (R)
BIT LO5-0 LE HE
HE 0
NAME Left Channel Output Attenuation Setting Line Output Enable Headphone Output Enable
VALUE FUNCTION 1 1 1 1 1 1 63 R 1.5dB attenuation steps. LO5 is the MSB. 0 = no attenuation. 111111 = -94.5dB 0 R Analog line outputs off (muted). 1 Analog line outputs on. 0 R Headphone output off (muted). 1 Headphone output on. DS76F2
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CS4215
Data Time Slot 6, Output Setting
D7 D6 SE 0 D5 RO5 1 D4 RO4 1 D3 RO3 1 D2 RO2 1 D1 RO1 1 D0 RO0 1
Register Reset (R)
BIT RO5-0
ADI 1
SE ADI
NAME Right Channel Output Attenuation Setting Speaker Enable A/D Data Invalid
VALUE FUNCTION 1 1 1 1 1 1 63 R 1.5dB attenuation steps. RO5 is the MSB. 0 = no attenuation. 111111 = -94.5dB Not used in mono modes. R Speaker off (muted). 0 Speaker on. 1 0 A/D data valid. R A/D data invalid. Busy in calibration. 1
Data Time Slot 7, Input Setting
D7 D6 PIO0 1 D5 OVR 0 D4 IS 0 D3 LG3 0 D2 LG2 0 D1 LG1 0 D0 LG0 0
Register Reset (R)
BIT LG3-0 IS OVR
PIO1 1
NAME Left Channel Input Gain Setting Input Select Overrange
VALUE 0000 0 1 0
R R R
PIO1-0
Parallel I/O
11
3
R
FUNCTION 1.5dB gain steps. LG3 is the MSB. 0 = no gain, 1111 = 22.5dB gain. Line level inputs (LINL, LINR). Microphone level inputs (MINL, MINR). When read as 1, this bit indicates that an input overrange condition has occurred. The bit remains set until cleared by writing 0 into the register. Writing a 1 enables the overrange detection. The bit will remain 0 until an over-range occurs. Serial port clear has priority over internal settings. Parallel input/output bits.
Data Time Slot 8, Input Setting
D7 D6 MA2 1 D5 MA1 1 D4 MA0 1 D3 RG3 0 D2 RG2 0 D1 RG1 0 D0 RG0 0
Register Reset (R)
BIT RG3-0 MA3-0
MA3 1
NAME Right Channel Input Gain Setting Monitor Path Attenuation
VALUE 0000 1111
FUNCTION R 1.5dB gain steps. RG3 is the MSB. 0 = no gain, 1111 = 22.5dB gain. 15 R 6dB attenuation steps. MA3 is the MSB. 0 = no attenuation, 1111 = mute.
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23
ADI SE
LSB HE LE
MSB
16 Bit Mono
LSB HE LE ADI SE OVR IS LO RO PIO LG MA
8 Bit Stereo
LSB ADI SE MSB OVR IS RIGHT HE LE LO RO PIO LG MA RG
MSB
LEFT CHANNEL AUDIO
8 Bit Mono
HE LE ADI SE OVR IS LO RO PIO LG MA
MSB
Control Mode
ST ITS XCLK XEN ENL DAD DF BSEL MCK TEST PIO VERSION
MSB
MLB OLB CLB
HPF
001
LSB
LEFT
LSB
LEFT
DFR
LSB MSB
OVR IS
24 3
RIGHT CHANNEL AUDIO LO PIO RO LG
1 16 Bit Stereo
2
4
5
6
7
MA
8
RG
LEFT CHANNEL AUDIO
CS4215
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Figure 1 5. Time Slot/Register Overview
CS4215
C S4215
A/ D e co d e LOUT D /A A tte n u a tio n ROUT (S till O p e ra te ) D ig ita l-
SDIN DAD DD
D ig ita l-D igita l L o o p b a ck
M o n ito r = 1 1 1 1 (Full M ute)
A n a lo g -
D ig ita l
L o o p b a ck
SDOUT
A/ E n co d e
LIN A/D G a in R IN (D isco n n e cte d )
C S4215 A/ D ecod e LO UT D /A A tte n ua tio n
SDIN (D A C d a ta = 0 ) 0 is d iffe re n t fo r
ROUT
e a ch d a ta
format M o n ito r = 0
ADA SDOUT A/ E n co d e LIN A /D G a in R IN
Figure 16. DD, DAD & ADA Loopback Paths
Power Down Mode Bringing the PDN pin high puts the CS4215 into the power down mode. In this mode HEADC and CMOUT will not supply current. Power down will change all the control registers to the reset state shown under each Control Time Slot register. In the power down mode, the TSOUT pin will follow the TSIN state with less than 10 ns delay. After returning to normal operation from power down, an offset calibration cycle must be executed. Either bringing RESET low then high, or updating the control registers, will cause an offset calibration cycle. In either case, a delay of 50 ms must occur after PDN goes low before executing the offset calibration. This allows the internal voltage reference time to settle.
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LOOPBACK TEST MODES The CS4215 contains three loopback modes that may be used to test the codec. Two of the loopback test modes are designed to allow the host to perform a self-test on the CS4215. The third mode allows laboratory testing using external equipment. Host Self-Test Loopback Modes Since the CS4215 is a mixed-signal device, it is equipped with an internal register that will enable the host to perform a two-tiered test on power-up or as needed. The loopback test is enabled by setting the Enable Loopback bit, ENL, in control register 4. The first tier of loopback is a digital-digital loopback, DD, which is selected by clearing the DAD bit in control register 4 (see
25
CS4215 Figure 16). DD loopback checks the interface between the host and the CS4215 by taking the data on SDIN and looping it back onto SDOUT, with the data on SDOUT being one frame delayed from the data on SDIN. The host can verify that the data received is exactly the same as the data sent, thereby indicating the interface between the two devices and the digital interface on the CS4215 are operating properly. The output DAC's are functional in DD loopback. Now that the interface has been verified, the rest of the CS4215 can be tested using the second tier of loopback. The second tier of loopback is a digital-analogdigital loopback, DAD, which is selected by setting the DAD bit in control register 4. DAD loopback checks the analog section of the CS4215 by connecting the right and left analog outputs, after the output attenuator, to the analog inputs of the gain stage. This allows testing of most of the CS4215 from the host by sending a known digital signal to the DACs and monitoring the digital signal from the ADCs. During DAD loopback, the monitor attenuator must be set at maximum (full mute), and the analog outputs may be individually muted. The analog inputs are disconnected internally. The flow of test data for both DD and DAD loopback modes is illustrated in the top portion of Figure 16.
Ferrite Bead +5V Supply 2.0 + 1 uF 0.1 uF 1 uF 3 VD1 8 VD2 23 24 VA1 VA2 + 0.1 uF 0.1 uF + 1 uF
Analog-to-Analog Loopback Mode A third loopback mode is achieved by setting the monitor attenuator to zero attenuation and sending the DACs digital zero via SDIN. This loopback is termed analog-digital-analog, ADA, since the selected analog input will now appear on the enabled analog outputs. Since this test is controlled by external stimulus and the host is not involved (except to send the DACs zeros), it is generally considered a laboratory test as opposed to a self test. The bottom portion of Figure 16 illustrates the ADA signal flow through the CS4215. Note that this test requires the host send analog zeros to the DAC. Each data format has a different code for zero. See Figures 13 and 14.
CS4215
Figure 17. Optional Power Supply Arrangement
26
DS76F2
CS4215
> 1/8"
Digital Ground Plane
Ground Connection +5V Ferrite Bead
Analog Ground Plane CS4215
Note that the CS4215 is oriented with its digital pins towards the digital end of the board.
CPU & Digital Logic
Codec digital signals
Codec analog signals & Components
Figure 18. Suggested Layout Guideline
POWER SUPPLY AND GROUNDING When using separate supplies, the digital power should be connected to the CS4215 via a ferrite bead, positioned closer than 1" to the device (see Figure 1). The codec VA1, VA2 pins should be derived from the cleanest power source available. If only one supply is available, use the suggested arrangement in Figure 17. VA1 supplies analog power to the ADCs and DACs while VA2 supplies p ower to the output power drivers (headphones and speaker). The large currents necessary for VA2 are not flowing through the 2.0 resistor, and therefore do not corrupt the VA1 converter supply. The CS4215 along with associated analog circuitry, should be positioned near to the edge of the circuit board, and have its own, separate, ground plane. On the CS4215, the analog and digital grounds are internally connected; therefore, the four ground pins must be externally connected with zero impedance between ground pins. The best solution is to place the entire chip
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on a solid ground plane as shown in Figure 18. Preferably, it should also have its own power plane. A single connection between the CS4215 ground and the board ground should be positioned as shown in Figure 18. Figure 19 illustrates the optimum ground and decoupling layout for the CS4215 assuming a surface-mount socket and leaded decoupling capacitors. Surface-mount sockets are useful since the pad locations are exactly the same as the actual chip; therefore, given that space for the socket is left on the board, the socket can be optional for production. Figure 19 depicts the top layer containing signal traces and assumes the bottom or inter-layer contains a solid analog ground plane. The important points with regards to this diagram are that the ground plane is SOLID under the codec and connects all codec ground pins with thick traces providing the absolute lowest impedance between ground pins. The decoupling capacitors are placed as close as possible to the device which, in this case, is the socket boundary. The lowest value capacitor is
27
CS4215
0.1 u F
1 uF
1
+
Analog Supply
0.1 uF
1 uF +
Figure 19. CS4215 Decoupling Layout Guideline
0.1 uF
0.1 uF
1 uF
10 uF
Digital Supply
+
1 +
Analog Supply
0.1 uF
0.1 u F +
Digital Supply
10 uF
+
1 uF
Figure 20. CS4215 Surface Mount Decoupling Layout 28 DS76F2
CS4215 placed closest to the codec. Vias are placed near the AGND and DGND pins, under the IC, and should be attached to the solid analog ground plane on another layer. The negative side of the decoupling capacitors should also attach to the same solid ground plane. Traces bringing the power to the codec should be wide thereby keeping the impedance low. Although not shown in the figures, the trace layers (top layer in the figures) should have ground plane fill in-between the traces to minimize coupling into the analog section. See the CDB4215 evaluation board data sheet for an example layout. If using all surface-mount components, the decoupling capacitors should still be placed on the layer with the codec and in the positions shown in Figure 20. The vias shown are assumed to attach to the appropriate power and analog ground layers. Traces bringing power to the codec should be as wide as possible to keep the impedance low. For the same reason, vias should be large for power and ground runs. If using through-hole sockets, effort should be made to find a socket with the minimum height which will minimize the socket impedance. When using a through-hole socket, the vias under the codec in Figure 19 are not needed since the pins serve the same function. ADC and DAC Filter Response Plots
Magnitude (dB) 10 0 -10 Magnitude (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Frequency (Fs) 0.8 0.9 1.0
Figure 21. ADC Frequency Response
0.2 0.1 -0.0 Magnitude (dB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (Fs)
Figure 22. ADC Passband Ripple
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Input Frequency (Fs)
Figures 21 through 27 show the overall frequency response, passband ripple and transition band for the CS4215 ADCs and DACs. Figure 27 shows the DACs' deviation from linear phase. Fs is the selected sample frequency. Since the sample frequency is programmable, the filters will adjust to the selected sample frequency. Fs is also the FSYNC frequency.
Figure 23. ADC Transition Band DS76F2 29
CS4215
10 0 -10 Magnitude (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Input Frequency (Fs) 0.8 0.9 1.0 Magnitude (dB)
0.2 0.1 -0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (Fs)
Figure 24. DAC Frequency Response
Figure 25. DAC Passband Ripple
0 -10 Magnitude (dB) -20 Phase (degrees) -30 -40 -50 -60 -70 -80 -90 -100 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Input Frequency (Fs)
2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (Fs)
Figure 26. DAC Transition Band
Figure 27. DAC Deviation from Linear Phase
30
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CS4215 PIN DESCRIPTIONS
CLKOUT DGND1 SDOUT XTL1IN FSYNC TSOUT 79 CLKIN
SCLK
SDIN
100
97
95
93
91
89
87
85
83
81
77 76 75 74
XTL1OUT VD2 DGND2 XTL2IN XTL2OUT
1 2 4 6 8 10
TSIN
VD1
PIO1 PIO0 D/C
CS4215 100-PIN TQFP (Q) Top View
72 70
66 64
LOUTR LOUTL
RESET PDN MINR LINR MINL LINL
14 16 18 20 22 24 25 26 31 33 35 37 39 41 43 45 50 52 51 HEADR 56 HEADC 60 HEADL
VA1
VREF
VA2
MOUT2
Note: All unlabeled pins are No Connects
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CMOUT
MOUT1
AGND1
AGND2
31
CS4215
SDIN DGND1 VD1 CLKIN CLKOUT XTL1IN XTL1OUT VD2 DGND2 XTL2IN XTL2OUT RESET PDN NC MINR LINR MINL LINL CMOUT NC VREF AGND1
7 8 9 10 11 12 13 14 15 16 17
6
4
2 1 44
42
40
CS4215 44-PIN PLCC (L) Top View
18 20 22 24 26 28
39 38 37 36 35 34 33 32 31 30 29
SDOUT SCLK FSYNC TSOUT TSIN NC NC PIO1 PIO0 D/C NC LOUTR LOUTL HEADL HEADC HEADR MOUT1 MOUT2 NC AGND2 VA2 VA1
Power Supply VA1, VA2 - Analog Power Input, Pins 23(L), 24(L), 37(Q), 39 (Q) +5 V analog supply. AGND1, AGND2 - Analog Ground, Pins 22(L), 25(L), 35(Q), 41(Q) Analog ground. Must be connected to DGND1, DGND2 with zero impedance. VD1, VD2 - Digital Power Input, Pins 3(L), 8(L), 91(Q), 4(Q) + 5 V digital supply. DGND1, DGND2 - Digital Ground, Pin 2(L), 9(L), 89(Q), 6(Q) Digital ground. Must be connected to AGND1, AGND2 with zero impedance.
32
DS76F2
CS4215 Analog Inputs LINL, LINR - Left and Right Channel Line Level Inputs, Pins 18(L), 16(L), 24(Q), 20(Q) Line level input connections for the right and left channels. MINL, MINR - Left and Right Channel Microphone Inputs, Pins 17(L), 15(L), 22(Q), 18(Q) Microphone level input connections for the right and left channels. Analog Outputs LOUTR, LOUTL - Line Level Outputs, Pins 33(L), 32(L), 66(Q), 64(Q) One pair of line level outputs are provided. The output level for right and left outputs can be independently varied. These outputs can be muted. HEADR, HEADL - Headphone Outputs, Pins 29(L), 31(L), 52(Q), 60(Q) HEADR and HEADL are intended to drive a pair of headphones. Additional current drive, along with an optional +3 dB of gain, ensures reasonable listening levels. These outputs can be muted. HEADC - Common Return for Headphone Outputs, Pin 30(L), 56(Q) HEADC is the return path for large currents when driving headphones from the HEADR and HEADL outputs. This pin is nominally at 2.1 V. CMOUT - Common Mode Output, Pin 19(L), 31(Q) Common mode voltage output. This signal may be used for level shifting the analog inputs. The load on CMOUT must be DC only, with an impedance of not less than 10k. CMOUT should be bypassed with a 0.47 F to AGND. CMOUT is nominally at +2.1V. MOUT1, MOUT2 - Mono Speaker Outputs, Pins 28(L), 27(L), 45(Q), 43(Q) Mono external loudspeaker differential output connections. The loudspeaker output is a mix of left and right line outputs. Independent muting of the speaker is provided. MOUT1 and MOUT2 output voltage is nominally at 2.1 V with no signal. VREF - Voltage Reference Output, Pin 21(L), 33(Q) The on-chip generated ADC/DAC reference voltage is brought out to this pin for decoupling purposes. This output must be bypassed with a 10 F capacitor in parallel with a 0.1 F capacitor to the adjacent AGND1 pin. No other external load may be connected to this output. Digital Interface Signals SDIN - Serial Data Input, Pin 1(L), 87(Q) Audio data for the DACs and control information for all functions is presented to the CS4215 on this pin. SDOUT - Serial Data Output, Pin 44(L), 85(Q) Audio data from the ADCs and status information concerning all functions is written out by the CS4215 onto this pin.
DS76F2 33
CS4215 SCLK - Serial Port Clock, Pin 43(L), 83(Q) SCLK rising causes the data on SDOUT to be updated. SCLK falling latches the data on SDIN into the CS4215. The SCLK signal can be generated off-chip, and input into the CS4215. Alternatively, the CS4215 can generate and output SCLK in data mode. FSYNC - Frame Sync Signal, Pin 42(L), 81(Q) The Frame Synchronizing Signal is sampled by SCLK, with a rising edge indicating a new frame is about to start. FSYNC frequency is always the system sample rate. Each frame may have 64, 128 or 256 data bits, allowing for 1, 2 or 4 CS4215s connected to the same bus. FSYNC may be input to the CS4215, or may be generated and output by the CS4215 in data mode. When FSYNC is an input, it must be high for at least 1 SCLK period. FSYNC can stay high for the rest of the frame, but must return low at least 2 SCLKs before the next frame starts. TSIN - Time Slot Input, Pin 40(L), 77(Q) TSIN high for at least 1 SCLK cycle indicates to the CS4215 that the next time slot is allocated for it to use. TSIN is normally connected to the TSOUT pin of the previous device in the chain. TSIN should be connected to FSYNC for the 1st (or only) CS4215 in the chain. TSOUT - Time Slot Output, Pin 41(L), 79(Q) TSOUT goes high for 1 SCLK cycle, indicating that the CS4215 is about to release the data bus. Normally connected to the TSIN pin on the next device in the chain. D/C - Data/Control Select Input, Pin 35(L), 70(Q) When D/C is low, the information on SDIN and SDOUT is control information. When D/C is high, the information on SDIN and SDOUT is data information. PDN - Power Down Input, Pin 13(L), 16(Q) When high, the PDN pin puts the CS4215 into the power down mode. In this mode HEADC and CMOUT will not supply current. Power down causes all the control registers to change to the default reset state. In the power down mode, the TSOUT pin remains active, and follows TSIN delayed by less than 10 ns. RESET - Active Low Reset Input, Pin 12(L), 14(Q) Upon reset, the values of the control information (when D/C = 0) will be initialized to the values given in the Reset Description section of this data sheet. Clock and Crystal Pins XTL1IN, XTL1OUT, XTL2IN, XTL2OUT - Crystals 1 and 2 Inputs and Outputs, Pins 6(L), 7(L), 10(L), 11(L), 97(Q), 2(Q), 8(Q), 10(Q) Input and output connections for crystals 1 and 2. One of these oscillators may provide the master clock to run the CS4215. CLKIN - External Clock Input, Pin 4(L), 93(Q) External clock input optionally used to clock the CS4215. The CLKIN frequency must be 256 times the maximum sample rate (FSYNC frequency).
34 DS76F2
CS4215 CLKOUT - Master Clock Output, Pin 5(L), 95(Q) Master clock output, whose frequency is always 256 times the system sample rate (FSYNC frequency). CLKOUT is active only in data mode and is low during control mode. Miscellaneous Pins PIO0, PIO1 - Parallel Input/Output, Pins 36(L), 37(L), 72(Q), 74(Q) These pins are provided as general purpose digital parallel input/output and have open drain outputs. An external pull-up resistor is required. They can be read in control mode, and read and written to in data mode. Note: All unlabeled pins are No Connects which should be left floating.
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35
CS4215 PARAMETER DEFINITIONS
Resolution The number of bits in the input words to the DACs, and in the output words in the ADCs. Differential Nonlinearity The worst case deviation from the ideal codewidth. Units in LSB. Total Dynamic Range The rms value of a full scale signal to the lowest obtainable noise floor. It is measured by comparing a full scale signal to the lowest noise floor possible in the codec (ie. attenuation bits for the DACs at full attenuation.) Units in dB. Instantaneous Dynamic Range The dynamic range available at any instant in time. It is measured using S/(N+D) with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal. Use of a small input signal reduces to harmonic distortion components of the noise to insignificance. Units in dB. Total Harmonic Distortion THD is the ratio of the rms value of a signal's first five harmonic components to the rms value of the signals fundamental component. THD is calculated for the ADCs using an input signal which is 3dB below typical full-scale, and is referenced to typical full-scale. A digital full-scale output is used to calculate THD for the DACs. Interchannel Isolation The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz 0 dB signal present on the other channel. Units in dB. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units in dB. Frequency Response Worst case variation in output signal level versus frequency over 10 Hz to 20 kHz. Units in dB. Step Size Typical delta between two adjacent gain or attenuation values. Units in dB. Absolute Step Error The deviation of a gain or attenuation step from a straight line passing through the no-gain/attenuation value and the full-gain/attenuation value (i.e. end points). Units in dB.
36
DS76F2
CS4215
Out-of-Band Energy The ratio of the rms sum of the energy from 0.46xFs to 2.1xFs compared to the rms full-scale signal value. Tested with 48kHz Fs giving an out-of-band energy range of 22kHz to 100kHz. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input at CMOUT. For the DACs, the deviation of the output from CMOUT with mid-scale input code. Units in volts.
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37
CS4215 APPENDIX A This data sheet describes version 2 of the CS4215. Therefore, this appendix is included to describe the differences between versions 0,1 and version 2. This information is only useful for users that still have version 0 and version 1 devices since version 2 devices will supplant the earlier versions. The version number can be found in control mode, time slot 7. The version can also be identified by the revision letter stamped on the top of the actual chip. The revision letter immediately precedes the data code on the second line of the package marking (See General Information section of the Crystal Data Book). Version 0 corresponds to chip revision C, version 1 corresponds to chip revision D, and version 2 corresponds to chip revision E. Future chip revisions (ie. F, G, H) may still be version 2 since the version number only changes if there is a register change to the part that will affect driver software. The Functional Differences Between Version 0(Rev. C) and Version 1(Rev. D) 1. FSYNC on version 0 must be ONLY one SCLK period high, whereas on version 1 FSYNC must be AT LEAST one SCLK period high. 2. When driving an external CMOS clock into one of the XTL-IN pins, version 0 devices must have a series resistor of at least 1k between the CS4215 and the clock source. The resistor is needed because the codec will put XTL-IN to ground (on version 0 only) when that crystal is not selected, as is the case on power-up. In version 1 the XTL-IN pins are floated when not selected; therefore, the series resistor is not needed on version 1. Version 1 will work properly if the resistor is included. 3. The OLB and ITS bits do not exist on version 0. Writing these bits as zero makes both versions function identically; therefore, version 1 is backwards compatible with version 0. 4. When entering control mode, CLKOUT stops 4 to 12 clocks later and may start up briefly when switching master clock sources on version 0. On version 1 CLKOUT stops within two clocks and doesn't start up until data mode is entered. 5. In version 0 the headphone and speaker outputs are not short-circuit protected, whereas in version 1 they are short-circuited protected. The functional differences between Version 1(Rev. D) and Version 2(Rev. E) 1. The MLB, HPF, and MCK2 bits in control mode do not exist in version 0 or version 1. Writing these bits as zero makes all versions functionally identical; therefore, version 2 is backwards compatible with previous versions. 2. The A/D invalid bit, ADI, in data mode does not exist in version 0 or version 1. 3. The 8-bit unsigned data format (DF1,0=3) does not exist in version 0 or version 1. 4. SDOUT contained random data during calibration in versions 0 and 1. SDOUT outputs zeros during calibration in version 2.
38
DS76F2
Semiconductor Corporation
CDB4215
General Description
The CDB4215 evaluation board allows easy evaluation of the CS4215 audio multimedia codec. Analog inputs provided include two 1/4" microphone jacks and two BNC line inputs. Analog outputs provided are two BNC line outputs, one stereo 1/4" headphone jack and one pair of speaker terminals. Digital interfacing is facilitated by two buffered ribbon cable headers. One contains the serial port and the other contains the codec control pins.
CS4215 Evaluation Board
Features
*
Easy DSP Hook-Up
* Correct Grounding and Layout * Microphone Pre-Amplifier * Line Input Buffer * Digital Patch Area
+5VA Microphone Jacks
ORDERING INFORMATION: CDB4215
AGND
DGND +5VD
A = 23 dB
CLKOUT
CLKIN Line Inputs
A = - 6 dB
CS4215 Line Outputs Headphone Jack Speaker Terminals
Digital I/O Buffers
Control Pin Header Serial Port Header Digital Patch Area
PIO Indicators
Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 Fax: (512) 445 7581
Copyright (c) Crystal Semiconductor Corporation 1992 (All Rights Reserved)
JUL '93 DS76DB3 39
CDB4215 GENERAL INFORMATION The CDB4215 is designed to provide an easy platform for evaluating the performance of the CS4215 Multimedia Audio Codec. The board provides a buffered serial interface for easy connection to the serial port of a DSP or other serial device. A single +5 V power supply is all that is required to power the evaluation board. The line input buffers are designed to accept standard CD-level inputs of 2 VRMS and BNCto-phono adapters are included to support various test setups. The microphone inputs consist of two 1/4" mono jacks that are designed to accept standard single-ended dynamic or condenser microphones. The line outputs are supplied via BNC jacks with two more BNC-to-phono adapters. The headphone output is supplied via a 1/4" stereo jack and will drive headphones of 48 or greater. This includes most "walkman" style headphones. Speaker terminals are provided and can be connected to speakers with an impedance of 32 or greater. The film plots of the board are included to provide an example of the optimum layout, grounding, and decoupling arrangement for the CS4215. header buffer circuitry. Space for a ferrite bead inductor, L1, has been provided so that the board may be modified to power the codec from the digital supply. Selection of L1 will depend on the characteristics of the noise on the digital supply used.
ANALOG INPUTS The analog inputs consist of a pair of 1/4" jacks for two microphones, and a pair of BNC's for line level inputs. BNC-to-phono adapters are included to allow testing of the line inputs using coax or standard audio cables. The line-level inputs go through a buffer, Figure 2, with a gain of 0.5 which allows input signals of up to 2 VRMS. The two microphone inputs are single-ended and are designed to work with both condenser and dynamic mics. The microphone input buffer circuit, shown in Figure 3, has a gain of 23 dB thereby defining a full-scale input voltage to the mic jacks of 19.5 mVpp.
ANALOG OUTPUTS The CDB4215 includes three analog output paths: a pair of line output BNC's, a stereo 1/4" headphone jack, and a pair of mono speaker terminals. The CS4215 drives the line outputs into an R-C filter and then to a pair of BNC's. As with the line inputs, BNC-to-phono adapters are provided for flexibility. The line outputs can drive an impedance of 10 k or more, which is the typical input impedance of most audio gear. The stereo headphone output can drive headphones with an impedance of 48 or greater. This includes most "walkman" style headphones.
DS76DB3
POWER SUPPLY CIRCUITRY Figure 1 illustrates a portion of the CDB4215 schematic and includes the CS4215 codec along with power supply circuitry. Power is supplied to the board via two sets of binding posts, one for digital and one for analog. The analog supply must be +5 Volts and supplies power for the entire codec (both digital and analog power supply pins) along with the analog input buffers for the line and microphone inputs. The digital supply is also +5 Volts and supplies power to the digital
40
CDB4215
+5VD
VD
Ferrite Bead L1
R28 2
VA
+5VA
D2 P6KE
+ 47 uF C32
0.1 uF C30
+ 1 uF C14
0.1 uF C13
+ 1 uF C11
0.1 uF C12
0.1 uF C31
47 uF + C33
D1 P6KE
DGND AGND 3 15 19 17 8 23 24 28 C34 R52 50 k R51 50 k MOUT2 MOUT1 VD1 VD2 Microphone Input Buffer See Figure 3 MINR CMOUT MINL VA1 VA2 MOUT1 + 22 uF C16
16 Line Input Buffer See Figure 2 40pF C24 16.9344 MHz 40pF C25 40pF C22 24.576 MHz 40pF C23 7 18
LINR LINL
CS4215 U1
27 MOUT2 + 29
22 uF 16 1/2W
HEADR
10 XTL2IN Y2 11 XTL2OUT 6 Y1
HEADL HEADC
R21 31 R20 30 16 1/2W R24 600
Headphones
C29 1 uF + C27 C28 1 uF + C26
LOUTR 39 k R26 LOUTL 39 k R27
LOUTR XTL1IN
33
0.0022 uF NPO R25 600
XTL1OUT
LOUTL
32
0.0022 uF NPO 4 CLKIN 21 VREF 0.1 uF C21
See Fig 5
+ 10 uF C20
AGND1 AGND2 22 25
DGND1 DGND2 2 9
Figure 1. CS4215 & Power Supplies
DS76DB3
41
CDB4215
C19 R19 LINR 0.47 uF 20 k R12 56 pF NPO VA 10 k C36 0.1 uF 2_ 3+ 8 4 1 150 R14 5k + 1 uF C35 LINL (Mono) 0.47 uF 5 20 k R13 + 6_ R18 7 150 R15 C37 10 k C9 0.01 uF NPO 18 R17 16 0.01 uF NPO C10 19 CS4215 LINR
C17
U3 LT1013
CMOUT
LINL
C18
56 pF NPO
Figure 2. Line Input Buffer
R6 1.5 k 10 uF + C6 VA+ 2 + MINR C5 R5 50 k R2 50 k 5 + 1 uF 6 3
R4 22.1 k C4 560 pF NPO 8 4 1 U2 MC33178 C8 0.1 uF R56 150 C47 C48 0.47 uF NPO 0.01 uF 19 C7 + 1 uF R57 150 C1 560 pF NPO C46 NPO 0.01 uF C45 17 0.47 uF MINL CS4215 15 MINR
1 uF
CMOUT
MINL (Mono)
C2
7
1.5 k R3 10 uF + C3
22.1 k R1
Figure 3. Microphone Input Buffer
42
DS76DB3
CDB4215 Speaker terminals are provided and are labeled MOUT1 and MOUT2. Speakers connected to the terminals must have an impedance of 32 or greater. DC blocking capacitors are included to form a high-pass filter with the speaker impedance. This filter blocks very low frequency signals which can heavily distort some inexpensive speakers. mode. In control mode the codec is always a slave and FSYNC and SCLK must be driven from the DSP. Since the evaluation board buffers all the signals between the codec and the DSP, the board must "know" which of the two modes is being used. Jumper P3 selects the particular mode. Codec Master Data Mode SERIAL INTERFACE The CDB4215 is primarily designed to evaluate the CS4215 is single chip mode, i.e. only one codec on the serial bus. This is the default state for the CDB4215 and is defined by having the P4 jumper in the "1CHIP" position, see Figure 4, which connects FSYNC to TSIN. This connection defines the board codec's time slots as the first 64 bits of the frame. The only signals that need to be connected to the DSP are the five signals on header J15. The serial interface is illustrated in Figure 4. If the goal is to connect multiple CDB4215s on the same serial port, jumper P4 must be in the "MULTI" position which disconnects TSIN from FSYNC. The MULTI position also connects an unbuffered SDOUT to header J14. This header pin, SDOUTUB, must be used in lieu of SDOUT since SDOUT is buffered and does not go high impedance during other codec's time slots. Using the multi-chip scenario, the TSIN header pin must be connected to the previous codec's TSOUT line and the first codec's TSIN must be connected, via the header, to FSYNC. Note that when P4 is in the 1CHIP mode, the SDOUTUB pin on header J14 is not connected to the SDOUT pin on the CS4215 and is floating. There are two scenario's that must be addressed when connecting the CDB4215 to a DSP: one is when the codec is the master in data mode and the other is when the codec is a slave in data
DS76DB3
When the codec is to be programmed as a master in data mode, the direction of FSYNC and SCLK have to be changed between control mode and data mode. In this case the P3 jumper must be set for "M/S" which uses the D/C signal to control the direction of the buffers (U7) for SCLK and FSYNC. When P3 is set to M/S, the buffers drive the J15 header in data mode and receives FSYNC and SCLK from the header in control mode. Codec Slave Data Mode When the codec is to be programmed as a slave in data mode, FSYNC and SCLK are always inputs to the codec. In this mode P3 must be set to "SLAVE" which configures the FSYNC and SCLK buffers to always receive FSYNC and SCLK from the J15 header. As stated in the CS4215 data sheet, when the codec is programmed in slave mode, XCLK = 0 in control mode, SCLK and FSYNC are inputs and must be derived from the same clock used as the master clock for the codec. Although SCLK and FSYNC must be frequency locked to the master clock, there is no phase requirement.
CONTROL PINS All control pins, located on header J14, are defined as pins that are not essential to the DSP serial port when used in 1CHIP mode.
43
CDB4215
VD P3 M/S SLAVE SCLK FSYNC 43 42 R44 VD C40 1k R43 1k 13 11 OEB OEA A0 A1 A2 A3 GND 7 8 2 RP1 100 Ohm Dip 16 1 J15 D/C SDOUT SDIN TSIN TSOUT 44 1 40 41 3 16 15 6 7 17 4 5 14 13 R47 PDN CLKOUT 10 J14 13 5 12 9 8 11 20 k PIO0 PIO1 RESET SDOUTUB SDOUT SDIN SCLK FSYNC P4 1CHIP MULTI B0 10 B1 9 8 B2 B3 14 1 3 4 5 6
C41
0.1 uF
U7 74HCT243
RP2 20 k SIP
VD C49
1
0.1 uF
U1 CS4215
D/C 35
40 k R49 18
0.1 uF 20 2
TSIN TSOUT 9 8 PDN
U4 74HTC541
C42 0.1 uF RESET 12 8
R50 VD 50 R9 20 k 4 5 CLKOUT
14
10 6 9 VD
U5B
R42 100 R55 800 VD
U5C
7
D3 IN4148
R7 47 k C15 1 uF +
RESET 100
PIO0 237 k D3 Q2 R30 237 k
800
R54
R8
PIO1 D4 Q3
PIO0
36 37 Q2,Q3 = MPSA14
PIO1
R53
Figure 4. Digital Interface
44
DS76DB3
CDB4215 PDN and RESET Power down, PDN, controls the PDN pin on the codec. The line has an on-board pull-down resistor thereby defining the default state as powered. This pin only needs to be controlled if the power down feature is used. RESET controls the RESET pin on the codec and is pulled up on the board. This defines the default state as not reset. This pin only needs to be controlled if the reset feature on the codec is needed. Since the codec does require a reset at power up, a power-up reset circuit is included on the board. A reset switch is also included to reset the device without having to remove the power supply. The power-up reset plus switch are logically OR'ed with the RESET pin on header J14. PIO Lines The parallel input/output, PIO, lines are pulled up on the evaluation board. If they are to be used as inputs, they should be driven by open-collector gates since inadvertently setting the PIO bits low in software will force the external lines low. The PIO lines are available on header J14. The PIO lines also go through a high-impedance buffer and drive LED's on the evaluation board. When the LED is on, the corresponding bit is 1 or high. The LED's provide a visual indication that may be used to verify that the software is writing the bits correctly. CLOCKS The CDB4215 can accommodate all clocking modes supported by the CS4215. A CLKIN BNC, as shown in Figure 5 allows the CLKIN pin on the CS4215 to be used as the master clock source. The two crystals listed in the CS4215 data sheet are also provided and support all the audio and multimedia standard sample frequencies. The master clock is selected via a CS4215 internal register from control mode. The CLKOUT BNC is a buffered version of the CLKOUT pin on the CS4215. CLKOUT is always 256 times the programmed sample frequency in data mode. CLKOUT is held low in control mode.
LAYOUT ISSUES Figure 6 contains the silk screen, Figure 7 contains the top-side copper layer, and Figure 8 contains the bottom-side copper layer of the CDB4215 evaluation board. These plots are included to provide an example of how to layout a PCB for the codec. Two of the more important aspects are the position of the ground plane split, which is next to the part - NOT UNDER IT, and the ground plane fill between traces on both layers, which minimizes coupling of radiated energy.
CS4215
VD R16 10 k U5D 4 R32 1k 13 3 U5A 1 2 R29 5k CLKIN
CLKIN
11
12 74HC132
74HC132
Figure 5. CLKIN DS76DB3 45
CDB4215
Figure 6. CDB4215 Board Silkscreen (Not to Scale)
46
DS76DB3
CDB4215
Figure 7. CDB4215 Compont Side Layout (Not to Scale)
DS76DB3
47
CDB4215
Figure 8. CDB4215 Solder Side Layout (Not to Scale)
48
DS76DB3
44 pin PLCC
NO. OF TERMINALS
E1 E
MILLIMETERS INCHES
DIM
MIN NOM MAX 4.20 2.29 0.33 4.45 2.79 0.41
MIN NOM MAX
A A1
B
4.57 0.165 0.175 0.180 3.04 0.090 0.110 0.120 0.53 0.013 0.016 0.021
D/E 17.40 17.53 17.65 0.685 0.690 0.695
D1 D
D1/E1 16.51 16.59 16.66 0.650 0.653 0.656
D2/E2 14.99 15.50 16.00 0.590 0.610 0.630
e
1.19
1.27
1.35 0.047 0.050 0.053
B
e A1 D2/E2 A
D D1
100 pin TQFP
E
E1
1
C B e
A1
A
Terminal Detail 1
MILLIMETERS DIM A A1 B C D MIN 0.00 0.14 0.40 NOM 0.20 0.51 MAX 1.66 0.26 0.60
INCHES MIN NOM MAX 0.065
L M
0.000 0.008 0.010 0.006 0.016 0.020 0.024
15.70 16.00 16.30 0.618 0.630 0.642 13.90 14.00 14.10 0.547 0.551 0.555 15.70 16.00 16.30 0.618 0.630 0.642 13.90 14.00 14.10 0.547 0.551 0.555 0.375 0.30 0 0.5 0.51 1.00 BSC 0.625 0.015 0.020 0.025 0.70 12 0.012 0.020 0.028 0 12 0.039 BSC
D1 E E1
e L
M
* Notes *
Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation

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